AD8197B Datasheet | Analog Devices

FEATURES 4 inputs, 1 output HDMI/DVI links Enables HDMI 1.3-pliant receiver Pin-to-pin patible with the AD8197A 4 TMDS channels per link Supports 250 Mbps to 2.25 Gbps data rates Supports 25 MHz to 225 MHz pixel clocks Equalized inputs allow use of long HDMI cables .. (20 meters at 2.25 Gbps) Fully buffered unidirectional inputs/outputs Per input switchable, 50 Ω on-chip terminations Switchable output 50 Ω on-chip terminations Pre-emphasized outputs Low added jitter Single-supply operation (3.3 V) 4 auxiliary channels per link Bidirectional unbuffered inputs/outputs Flexible supply operation (3.3 V to 5 V) HDCP standard patible Allows switching of DDC bus and 2 additional signals Output disable feature Reduced power dissipation Removable output termination Allows building of larger arrays Two AD8197Bs support HDMI/DVI dual link Standards patible: HDMI receiver, HDCP, DVI Serial (I2C slave) and parallel control interface 100-lead, 14 mm × 14 mm LQFP, Pb-free package FUNCTIONAL BLOCK DIAGRAM PP_CH[1:0] PP_OTO PP_OCL PP_EQ PP_EN PP_PRE[1:0] RESET PARALLEL SERIAL I2C_SDA I2C_SCL I2C_ADDR[2:0] VTTI CONTROL LOGIC AVCC DVCC AMUXVCC AVEE DVEE VTTO CONFIG INTERFACE + IP_A[3:0] IN_A[3:0] - + IP_B[3:0] IN_B[3:0] - + IP_C[3:0] IN_C[3:0] - + IP_D[3:0] IN_D[3:0] - 4 4 4 4 4 4 4 4 4 4 SWITCH CORE EQ + OP[3:0] - ON[3:0] HIGH SPEED VTTI AUX_A[3:0] AUX_B[3:0] AUX_C[3:0] AUX_D[3:0] BUFFERED 4 4 4 4 SWITCH CORE LOW SPEED UNBUFFERED AUX_[3:0] BIDIRECTIONAL Figure 2. GENERAL DESCRIPTION The AD8197B is an HDMI™/DVI switch featuring equalized TMDS® inputs and pre-emphasized TMDS outputs, ideal for systems with long cable runs. The AD8197B offers individual control of the on/off state of the TMDS input termination resistors via I2C® control. Outputs can be set to a high impedance state to reduce the power dissipation and/or to allow the construction of larger arrays using the wire-OR technique. The AD8197B is provided in a 100-lead LQFP, Pb-free,...