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09278-001
Data Sheet
Low Jitter Clock Generator with 14 LVPECL/LVDS/HSTL/29 LVCMOS Outputs
AD9523-1
FEATURES
Output frequency: <1 MHz to 1 GHz Start-up frequency accuracy: <±100 ppm (determined by
VCXO reference accuracy) Zero delay operation
Input-to-output edge timing: <150 ps Dual VCO dividers 14 outputs: configurable LVPECL, LVDS, HSTL, and LVCMOS 14 dedicated output dividers with jitter-free adjustable delay Adjustable delay: 63 resolution steps of ½ period of VCO
output divider Output-to-output skew: <50 ps Duty cycle correction for odd divider settings Automatic synchronization of all outputs on power-up Absolute output jitter: <150 fs at 122.
AD9523-1 Datasheet
