AD9626 Datasheet | Analog Devices

FEATURES SNR = 64.8 d BFS @ f IN up to 70 MHz @ 250 MSPS ENOB of 10.5 @ f IN up to 70 MHz @ 250 MSPS (- 1.0 d BFS) SFDR = 80 d Bc @ f IN up to 70 MHz @ 250 MSPS (- 1.0 d BFS) Excellent linearity DNL = ±0.3 LSB typical INL = ±0.7 LSB typical CMOS outputs .. Single data port at up to 250 MHz Interleaved dual port @ ½ sample rate up to 125 MHz 700 MHz full power analog bandwidth On-chip reference, no external decoupling required Integrated input buffer and track-and-hold Low power dissipation 272 m W @ 170 MSPS 364 m W @ 250 MSPS Programmable input voltage range 1.0 V to 1.5 V, 1.25 V nominal 1.8 V analog and digital supply operation Selectable output data format (offset binary, twos plement, Gray code) Clock duty cycle stabilizer Integrated data capture clock APPLICATIONS Wireless and wired broadband munications Cable reverse path munications test equipment Radar and satellite subsystems Power amplifier linearization FUNCTIONAL BLOCK DIAGRAM RBIAS PWDN AGND AVDD (1.8V) REFERENCE CML VIN+ VIN- TRACK-AND-HOLD ADC 12-BIT CORE CLK+ CLK- CLOCK MANAGEMENT 12 DRVDD DRGND OUTPUT 12 STAGING LVDS Dx11 TO Dx0 OVRA OVRB SERIAL PORT DCO+ 07099-001 DCO- RESET SCLK SDIO CSB Figure 1. GENERAL DESCRIPTION The AD9626 is a 12-bit monolithic sampling analog-to-digital converter optimized for high performance, low power, and ease of use. The product operates at up to a 250 MSPS conversion rate and is optimized for outstanding dynamic performance in wideband carrier and broadband systems. All necessary functions, including a track-and-hold (T/H) and voltage reference, are included on the chip to provide a plete signal conversion solution. The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are CMOS patible and support either twos plement, offset binary format, or Gray code. A data clock output is available for proper output data timing. Fabricated on an advanced CMOS process, the AD9626 is available in a 56-lead...