Datasheet Summary
Data Sheet AD9633
Quad, 12-Bit, 80 MSPS/105 MSPS/125 MSPS, Serial LVDS 1.8 V ADC
Features
- 1.8 V supply operation
- Low power: 100 mW per channel at 125 MSPS with scalable power options
- SNR = 71 dB (to Nyquist)
- SFDR = 91 dBc (to Nyquist)
- DNL = ±0.3 LSB (typical); INL = ±0.5 LSB (typical)
- Serial LVDS (ANSI-644, default) and low power, reduced signal option (similar to IEEE 1596.3)
- 650 MHz full power analog bandwidth
- 2 V p-p input voltage range
- Serial port control
- Full chip and individual channel power-down modes
- Flexible bit orientation
- Built-in and custom digital test pattern generation
- Multichip sync and clock divider
- Programmable output clock and data alignment
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