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AD9708 - 8-Bit/ 100 MSPS TxDAC D/A Converter

General Description

8-Bit, 100 MSPS+ TxDAC® D/A Converter AD9708 FUNCTIONAL BLOCK DIAGRAM +5V 0.1␮F REFLO +1.20V REF 0.1␮F REF IO FS ADJ RSET +5V DVDD DCOM CLOCK SLEEP COMP1 AVDD ACOM 50pF CURRENT SOURCE ARRAY SEGMENTED SWITCHES LATCHES AD9708 COMP2 0.1␮F IOUTA IOUTB CLOCK DIGITAL DATA INPUTS (DB7

Key Features

  • Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 8-Bit Resolution Linearity: 1/4 LSB DNL Linearity: 1/4 LSB INL Differential Current Outputs SINAD @ 5 MHz Output: 50 dB Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 20 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Packages: 28-Lead SOIC and 28-Lead TSSOP Edge-Triggered Latches Fast Settling: 35 ns Full-Scale Settling to 0.1%.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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a FEATURES Member of Pin-Compatible TxDAC Product Family 125 MSPS Update Rate 8-Bit Resolution Linearity: 1/4 LSB DNL Linearity: 1/4 LSB INL Differential Current Outputs SINAD @ 5 MHz Output: 50 dB Power Dissipation: 175 mW @ 5 V to 45 mW @ 3 V Power-Down Mode: 20 mW @ 5 V On-Chip 1.20 V Reference Single +5 V or +3 V Supply Operation Packages: 28-Lead SOIC and 28-Lead TSSOP Edge-Triggered Latches Fast Settling: 35 ns Full-Scale Settling to 0.1% APPLICATIONS Communications Signal Reconstruction Instrumentation PRODUCT DESCRIPTION 8-Bit, 100 MSPS+ TxDAC® D/A Converter AD9708* FUNCTIONAL BLOCK DIAGRAM +5V 0.1␮F REFLO +1.20V REF 0.1␮F REF IO FS ADJ RSET +5V DVDD DCOM CLOCK SLEEP COMP1 AVDD ACOM 50pF CURRENT SOURCE ARRAY SEGMENTED SWITCHES LATCHES AD9708 COMP2 0.