ADCLK948 Datasheet | Analog Devices

Two Selectable Inputs, 8 LVPECL Outputs, Si Ge Clock Fanout Buffer ADCLK948 Features 2 selectable differential inputs 4.8 GHz operating frequency 75 fs rms broadband random jitter On-chip input terminations 3.3 V power supply FUNCTIONAL BLOCK DIAGRAM LVPECL Q0 Q0 Q1 Q1 Q2 Q2 Q3 APPLICATIONS Low jitter clock distribution Clock and data signal restoration Level translation Wireless munications Wired munications Medical and industrial imaging ATE and high performance instrumentation VREF 0 REFERENCE Q3 Q4 Q4 Q5 Q5 Q6 Q6 Q7 V T0 CLK0 GENERAL DESCRIPTION The ADCLK948 is an ultrafast clock fanout buffer fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (Si Ge) bipolar process. This device is designed for high speed applications requiring low jitter. The device has two selectable differential inputs via the IN_SEL control pin. Both inputs are equipped with center tapped, differential, 100 Ω on-chip termination resistors. The inputs accept dc-coupled LVPECL, CML, 3.3 V CMOS (single-ended), and ac-coupled 1.8 V CMOS, LVDS, and LVPECL inputs. A VREFx pin is available for biasing ac-coupled inputs. .. CLK0 V T1 CLK1 CLK1 IN_SEL Q7 REFERENCE Figure 1. The ADCLK948 Features eight full-swing emitter coupled logic (ECL) output drivers. For LVPECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For ECL operation, bias VCC to ground and VEE to the negative supply. The output stages are designed to directly drive 800 m V each side into 50 Ω terminated to VCC - 2 V for a total differential output swing of 1.6 V. The ADCLK948 is available in a 32-lead LFCSP and specified for operation over the standard industrial temperature range of - 40°C to +85°C. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result...