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ADF4193 - Fast Settling PLL Frequency Synthesizer

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General Description

The ADF4193 frequency synthesizer can be used to implement local oscillators in the upconversion and downconversion sections of wireless receivers and transmitters.

Its architecture is specifically designed to meet the GSM/EDGE lock time requirements for base stations.

It consists of a low noise, digital phase frequency detector (PFD), and

Overview

Data Sheet Low Phase Noise, Fast Settling PLL Frequency Synthesizer.

Key Features

  • New, fast settling, fractional-N PLL architecture Single PLL replaces ping-pong synthesizers Frequency hop across GSM band in 5 µs with phase settled by 20 µs 0.5° rms phase error at 2 GHz RF output Digitally programmable output phase RF input range up to 3.5 GHz 3-wire serial interface On-chip, low noise differential amplifier Phase noise figure of merit:.
  • 216 dBc/Hz Loop filter design possible using ADIsimPLL™ Qualified for automotive.

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