ADIN1300 Description
This design integrates an energy efficient Ethernet (EEE) physical layer device (PHY) core with all associated mon analog circuitry, input and output clock buffering, management interface and subsystem registers, and MAC interface and control logic to manage the reset and clock control and . The ADIN1300 is available in a 6 mm × 6 mm, 40-lead lead frame chip scale package (LFCSP). The device operates with a minimum...
ADIN1300 Key Features
- 10BASE-Te/100BASE-TX/1000BASE-T IEEE 802.3 pliant
- MII, RMII, and RGMII MAC interfaces
- 1000BASE-T RGMII latency transmit <68 ns, receive <226 ns
- 100BASE-TX MII latency transmit <52 ns, receive <248 ns
- Programmable RGMII timing delay and drive current
- Robotics/motion control
- Time sensitive networking (TSN)
- Building automation
- Test and measurement
- Industrial internet of things (IoT)