Datasheet Details
| Part number | ADSP-21583 |
|---|---|
| Manufacturer | Analog Devices |
| File Size | 4.82 MB |
| Description | SHARC+ Dual-Core DSP |
| Datasheet |
 ADSP-21583 Datasheet
|
|
|
General Description
3
Arm Cortex-A5 Processor 5 SHARC Processor 6 SHARC+ Core Architecture 8 System Infrastructure 10 System Memory Map 11 Security
Key Features
- Dual enhanced SHARC+ high performance floating-point cores Up to 500 MHz per SHARC+ core Up to 5 Mb (640 kB) Level 1 (L1) SRAM memory per core with parity (optional ability to configure as cache) 32-bit, 40-bit, and 64-bit floating-point support 32-bit fixed point Byte, short-word, word, long-word addressed Arm Cortex-A5 core 500 MHz/800 DMIPS with NEON/VFPv4-D16/Jazelle 32 kB L1 instruction cache/32 kB L1 data cache 256 kB Level 2 (L2) cache with parity Powerful DMA system On-chip memory protec.