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DSP Microcomputer
ADSP-2186
FEATURES PERFORMANCE 25 ns Instruction Cycle Time 40 MIPS Sustained
Performance Single-Cycle Instruction Execution Single-Cycle Context Switch 3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle Multifunction Instructions Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 100 Cycle Recovery from Power-Down Condition Low Power Dissipation in Idle Mode
INTEGRATION ADSP-2100 Family Code Compatible, with Instruction
Set Extensions 40K Bytes of On-Chip RAM, Configured as
8K Words On-Chip Program Memory RAM and 8K Words On-Chip Data Memory RAM Dual Purpose Program Memory for Both Instruction and Data Storage Independent ALU, Multiplier/Accumulator and Barrel Shifter Computational Units Two Independent Data Address Generators P
ADSP-2186 Datasheet
