Download the ADUC824 datasheet PDF.
This datasheet also covers the ADU variant, as both devices belong to the same dual-channel 16-/24-bit adcs family and are provided as variant models within a single manufacturer datasheet.
General Description
TEMP SENSOR INTERNAL BANDGAP VREF PROG.
Key Features
High Resolution Sigma-Delta ADCs Two Independent ADCs (16- and 24-Bit Resolution) Programmable Gain Front End 24-Bit No Missing Codes, Primary ADC 13-Bit p-p Resolution @ 20 Hz, 20 mV Range 18-Bit p-p Resolution @ 20 Hz, 2.56 V Range Memory 8 KB On-Chip Flash/EE Program Memory 640 Bytes On-Chip Flash/EE Data Memory Flash/EE, 100 Year Retention, 100 Kcycles Endurance 256 Bytes On-Chip Data RAM 8051-Based Core 8051-Compatible Instruction Set (12.58 MHz Max) 32 kHz External Crystal, On-Chip Program.
Full PDF Text Transcription for ADUC824 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
ADUC824. For precise diagrams, and layout, please refer to the original PDF.
a MicroConverter ®, Dual-Channel 16-/24-Bit ADCs with Embedded FLASH MCU ADuC824 FUNCTIONAL BLOCK DIAGRAM AVDD AIN1 AIN2 MUX BUF PGA PRIMARY 24-BIT ⌺-⌬ ADC CURRENT SOURCE...
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AGRAM AVDD AIN1 AIN2 MUX BUF PGA PRIMARY 24-BIT ⌺-⌬ ADC CURRENT SOURCE MUX IEXC1 IEXC2 AVDD FEATURES High Resolution Sigma-Delta ADCs Two Independent ADCs (16- and 24-Bit Resolution) Programmable Gain Front End 24-Bit No Missing Codes, Primary ADC 13-Bit p-p Resolution @ 20 Hz, 20 mV Range 18-Bit p-p Resolution @ 20 Hz, 2.56 V Range Memory 8 KB On-Chip Flash/EE Program Memory 640 Bytes On-Chip Flash/EE Data Memory Flash/EE, 100 Year Retention, 100 Kcycles Endurance 256 Bytes On-Chip Data RAM 8051-Based Core 8051-Compatible Instruction Set (12.
ADUC824 Datasheet
