HMC832A Datasheet | Analog Devices

FEATURES RF bandwidth: 25 MHz to 3000 MHz 3.3 V supply Maximum phase detector rate: 100 MHz Ultralow phase noise - 110 d Bc/Hz in band (typical), f O at 1600 MHz Fractional figure of merit (FOM): - 226 d Bc/Hz 24-bit step size, 3 Hz typical resolution Exact frequency mode with 0 Hz frequency error Fast frequency hopping 40-lead, 6 mm × 6 mm LFCSP package: 36 mm2 APPLICATIONS Cellular infrastructure Microwave radios Wi Max, Wi Fi munications test equipment CATV equipment DDS replacement Military Tunable reference sources for spurious-free performance GENERAL DESCRIPTION The HMC832A is a 3.3 V, high performance, wideband, fractional-N, phase-locked loop (PLL) that features an integrated voltage controlled oscillator (VCO) with a fundamental frequency of 1500 MHz to 3000 MHz and an integrated VCO output divider (divide by 1, 2, 4, 6, … 62) that enables the HMC832A to generate continuous frequencies from 25 MHz to 3000 MHz. The integrated phase detector (PD) and Σ-Δ modulator, capable of operating at up to 100 MHz, permit wider loop bandwidths and faster frequency tuning with excellent spectral performance. Industry leading phase noise and spurious performance, across all frequencies, enable the HMC832A to minimize blocker effects, and to improve receiver sensitivity and transmitter spectral purity. A low noise floor (- 160 d Bc/Hz eliminates any contribution to modulator/mixer noise floor in transmitter applications. FUNCTIONAL BLOCK DIAGRAM LD/SDO SCK SDI LOCK DETECT CONTROL MODULATOR CAL SPI PROGRAMMING INTERFACE EN ÷1, 2, 4, 6, ...62 SEN RF_P RF_N ÷N CP CP PFD ÷R VTUNE XREFP Figure 1. The HMC832A is footprint patible to the HMC830 PLL with an integrated VCO. It features 3.3 V supply and innovative programmable performance technology that enables the HMC832A to tailor current consumption and corresponding noise floor performance to individual applications by selecting either a low current consumption mode or a high performance mode for improved...