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LTC6952 - Ultralow Jitter / 4.5GHz PLL

General Description

The LTC®6952 is a high performance, ultralow jitter, JESD204B/C clock generation and distribution IC.

It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, phase-frequency detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider.

Key Features

  • nn JESD204B/C, Subclass 1 SYSREF Signal Generation nn Low Noise Integer-N PLL nn Additive Output Jitter < 6fsRMS (Integration BW = 12kHz to 20MHz, f = 4.5GHz) nn Additive Output Jitter 65fsRMS (ADC SNR Method) nn EZSync™, ParallelSync™ Multichip Synchronization nn.
  • 229dBc/Hz Normalized In-Band Phase Noise Floor nn.
  • 281dBc/Hz Normalized In-Band 1/f Noise nn Eleven Independent, Low Noise Outputs with Programmable Coarse Digital and Fine Analog Delays nn Flexible Outputs Can Serve a.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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LTC6952 Ultralow Jitter, 4.5GHz PLL with 11 Outputs and JESD204B/JESD204C Support FEATURES nn JESD204B/C, Subclass 1 SYSREF Signal Generation nn Low Noise Integer-N PLL nn Additive Output Jitter < 6fsRMS (Integration BW = 12kHz to 20MHz, f = 4.