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MAX96752 - GMSL2 Deserializer

General Description

The MAX96752 deserializers convert a single- or dual-link GMSL™ serial input to single or dual OLDI.

They also send and receive side-channel and peripheral control data, enabling full-duplex, single-wire transmission of video and bidirectional data.

Key Features

  • 1 x 4, 2 x 4, or 1 x 8 OLDI Output Lane Configurations.
  • 3Gbps or 6Gbps Forward Link Rates for System and Power Flexibility.
  • Full-Duplex Capability Over a Single Wire.
  • Supports Up to 300MHz PCLK.
  • Supports Video Replication and Dual-View Splitting for Driving Two Displays.
  • Uses Low-Cost 50Ω Coax or 100Ω STP Cables.
  • Forward and Reverse I2S or 7.1 TDM Audio.
  • Optional Internal VDD Regulator.
  • ASIL-Relevant Functional Safety Features.
  • ASIL-B Compli.

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Other Datasheets by Analog Devices

Part Number Description
MAX96751 GMSL2 Serializer
MAX96714 Single GMSL2/GMSL1 to CSI-2 Deserializer
MAX96714F Single GMSL2/GMSL1 to CSI-2 Deserializer
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MAX96717 CSI-2 to GMSL2 Serializer

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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MAX96752 Click here to ask an associate for production status of specific part numbers. GMSL2 Deserializer with Dual LVDS (OLDI) Output General Description The MAX96752 deserializers convert a single- or dual-link GMSL™ serial input to single or dual OLDI. They also send and receive side-channel and peripheral control data, enabling full-duplex, single-wire transmission of video and bidirectional data. The OLDI output can be configured as single-port (4 or 8 lanes) or dual-port (2 x 4 lanes) for flexibility in driving displays with a variety of resolutions. Each port accommodates pixel clock rates of up to 150MHz, and in dual-port mode, the MAX96752 support a combined pixel clock of up to 300MHz. The GMSL2 concurrent control channel operates in I2C or UART mode.