SW06 Datasheet | Analog Devices

.. a Features Two Normally Open and Two Normally Closed SPST Switches with Disable Switches Can Be Easily Configured as a Dual SPDT or a DPDT Highly Resistant to Static Discharge Destruction Higher Resistance to Radiation than Analog Switches Designed with MOS Devices Guaranteed RON Matching: 10% max Guaranteed Switching Speeds T ON = 500 ns max T OFF = 400 ns max Guaranteed Break-Before-Make Switching Low “ON” Resistance: 80 ⍀ max Low R ON Variation from Analog Input Voltage: 5% Low Total Harmonic Distortion: 0.01% Low Leakage Currents at High Temperature T A = +125؇ C: 100 n A max T A = +85؇ C: 30 n A max Digital Inputs TTL/CMOS patible and Independent of V+ Improved Specifications and Pin patible to LF-11333/13333 Dual or Single Power Supply Operation Available in Die Form Quad SPST JFET Analog Switch SW06 FUNCTIONAL BLOCK DIAGRAM V+ 12 3 IN 1 S1 2 6 IN 2 8 LEVEL SHIFT 7 11 IN 3 9 10 14 IN 4 16 15 4 DIS 13 GND V- 5 D1 S2 D2 S3 D3 S4 D4 GENERAL DESCRIPTION The SW06 is a four channel single-pole, single-throw analog switch that employs both bipolar and ion-implanted FET devices. The SW06 FET switches use bipolar digital logic inputs which are more resistant to static electricity than CMOS devices. Ruggedness and reliability are inherent in the SW06 design and construction technology. Increased reliability is plemented by excellent electrical specifications. Potential error sources are reduced by minimizing “ON” resistance and controlling leakage currents at high temperatures. The switching FET exhibits minimal RON variation over a 20 V analog signal range and with power supply voltage changes. Operation from a single positive power supply voltage is possible. With V+ = 36 V, V- = 0 V, the analog signal range will extend from ground to +32 V. PNP logic inputs are TTL and CMOS patible to allow the SW06 to upgrade existing designs. The logic “0” and logic “1” input currents are at microampere levels reducing loading on CMOS and...