Description
CLK I
Clock
DAT0
I/O/PP
Data
DAT1
I/O/PP
Data
DAT2
I/O/PP
Data
DAT3
I/O/PP
Data
DAT4
I/O/PP
Data
DAT5
I/O/PP
Data
DAT6
I/O/PP
Data
DAT7
I/O/PP
Data
CMD
I/O/PP/OD
Command/Response
RST_n
I
Hardware reset
VCC S
Supply voltage for Core
VCCQ
S
Supply voltage for I/O
Features
- SDR Data sampling method.
- CLK frequency up to 200MHz Data rate.
- up to 200MB/s.
- 8-bits bus width supported.
- Single ended signaling with 4 selectable Drive Strength.
- Signaling levels of 1.8V.
- Tuning concept for Read Operations
1.3.2 HS200 System Block Diagram
Figure 2 shows a typical HS200 Host and Device system. The host has a clock generator, which supplies CLK to the Device. For write operations, clock and data direction are the.
P3204M2S5X2 Datasheet
