Applied Micro Circuits PPC405CR
The PPC405CR employs the IBM CoreConnect™ bus architecture. This architecture, as implemented on the PPC405CR, consists of a 64-bit, 133-MHz Processor Local Bus (PLB) and a 32-bit, 66-MHz On-Chip Peripheral Bus (OPB).| Part No. | PPC405CR |
|---|---|
| Datasheet | PPC405CR Download |
| Manufacturer | Applied Micro Circuits |
| Description | Power PC 405CR Embedded Processor |
| Buy | Stock & Price |
FEATURES
● Data Sheet PowerPC 405CR Embedded Processor PowerPC® 405 32-bit RISC processor core operating up to 266MHz - Memory Management Unit - 16KB instruction and 8KB data caches - Multiply-Accumulate (MAC) function, including fast multiply unit - Programmable Timers Synchronous DRAM (SDRAM) interface operating up to 133MHz - 32-bit interface for non-ECC applications - 40-bit interface serves 32 bits of data plus 8 check bits for ECC applications External Peripheral Bus - Flash ROM/Boot ROM interface - Direct support for 8-, 16-, or 32-bit SRAM and external peripherals - Up to eight devices - External Mastering supported● DMA support for external peripherals, internal UART and memory - Scatter-gather chaining supported - Four channels Programmable Interrupt Controller supports interrupts from a variety of sources - Supports 7 external and 10 internal interrupts - Edge triggered or level-sensitive - Positive or negative active - Non-critical or critical interrupt to processor core -...
