AZ100LVEL33 Description
The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q ¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state.
- Part: AZ100LVEL33
- Manufacturer: Arizona Microtek
- Size: 153.83 KB
Related Arizona Microtek Datasheets
| Part Number | Description |
|---|---|
| AZ100LVEL32 | ECL/PECL / 2 Divider |
| AZ100LVEL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ100LVEL16 | ECL/PECL Differential Receiver |
| AZ100LVEL16VS | ECL/PECL Differential Receiver |
| AZ100LVEL16VT | ECL/PECL Oscillator Gain Stage & Buffer |