AZ100LVEL33 datasheet by Arizona Microtek.
| Part number | AZ100LVEL33 |
|---|---|
| Datasheet | AZ100LVEL33_ArizonaMicrotek.pdf |
| File Size | 153.83 KB |
| Manufacturer | Arizona Microtek |
| Description | ECL/PECL / 4 Divider |
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The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q ¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state.
View all Arizona Microtek datasheets
| Part Number | Description |
|---|---|
| AZ100LVEL32 | ECL/PECL / 2 Divider |
| AZ100LVEL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ100LVEL16 | ECL/PECL Differential Receiver |
| AZ100LVEL16VS | ECL/PECL Differential Receiver |
| AZ100LVEL16VT | ECL/PECL Oscillator Gain Stage & Buffer |
| AZ100LVEL16VV | Dual Frequency ECL/PECL Oscillator Gain Stage & Buffer |
| AZ100LVEL58 | ECL/PECL 2:1 Multiplexer |
| AZ100LVE111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ100LVE111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ100LVE111E | ECL/PECL 1:9 Differential Clock Driver |
