The AZ10/100LVEL33 is an integrated ÷4 divider.
The RESET pin is asynchronous and clears the output (Q Low, Q ¯ High) on the rising edge.
Upon power-up, the internal flip-flop will be in a random logic state.
| Part number | AZ100LVEL33 |
|---|---|
| Manufacturer | Arizona Microtek |
| File Size | 153.83 KB |
| Description | ECL/PECL / 4 Divider |
| Datasheet |
 AZ100LVEL33 Datasheet
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| Part Number | Description | Manufacturer |
|---|---|---|
| AZ100LVEL16VR | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
| AZ100LVEL16VRL | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
| AZ100LVEL16VRLR1 | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
| AZ100LVEL16VRLR2 | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
| AZ100LVEL16VRX | ECL/PECL Oscillator Gain Stage & Buffer with Selectable Enable | ETC |
| Part Number | Description |
|---|---|
| AZ100LVEL32 | ECL/PECL / 2 Divider |
| AZ100LVEL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ100LVEL16 | ECL/PECL Differential Receiver |
| AZ100LVEL16VS | ECL/PECL Differential Receiver |
| AZ100LVEL16VT | ECL/PECL Oscillator Gain Stage & Buffer |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.
