AZ10E116 Datasheet | Arizona Microtek

FEATURES - - - - - 500ps Maximum Propagation Delay Dedicated VCCO Pin for Each Receiver Operating Range of 4.2V to 5.46V 75kΩ Internal Input Pulldown Resistors Direct Replacement for ON Semiconductor MC10E116 & MC100E116 PACKAGE PLCC 28 PLCC 28 1 2 PACKAGE AVAILABILITY PART NUMBER AZ10E116FN AZ100E116FN MARKING AZM10E116 <Date Code> AZM100E116 <Date Code> NOTES 1,2 1,2 Add R2 at end of part number for 13 inch (2.5K parts) Tape & Reel. Date code format: “YY” for year followed by “WW” for week. DESCRIPTION The AZ10/100E116 is a quint differential line receiver with emitter-follower outputs. The E116 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For single-ended input applications, the VBB reference should be connected to one side of the Dn/D ¯ n differential input pair. The input signal is then fed to the other Dn/D ¯ n input. The VBB pin should be used only as a bias for the E116 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF capacitor. The receiver design features clamp circuitry to cause a defined state if both the inverting and non-inverting inputs are left open; in this case the Q output goes LOW, while the Q ¯ output goes HIGH. This feature makes the device ideal for twisted pair applications. If both inverting and non-inverting inputs are at an equal potential of > VCC -2.5V, the receiver does not go to a defined state. This condition may produce output voltage levels between HIGH and LOW. NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established. 1630 S. STAPLEY DR., SUITE 127 - MESA, ARIZONA 85204 - USA - (480) 962-5881 - FAX (480) 890-2541 .azmicrotek. AZ10E116 AZ100E116 D3 25 D3 D2 D2 V EE V BB D0 D0 26 27 28 1 2 3 4 5 D1 6 D1 7 VCCO 8 Q0 9 Q0 10 VCCO D4 24 D4 23 V CCO 22 Q4 21 Q4 20 VCCO 19 18 17 LOGIC SYMBOL Q3 Q3 V CC Q2 Q2 D0 D0 D1 D1 Q0 Q0 Q1 Q1 Pinout: 28-lead PLCC (top view) 16 15 14 13 12 11...