This datasheet includes multiple variants, all published together in a single manufacturer document.
| Part number | AZ10LVEL33 |
|---|---|
| Datasheet | AZ10LVEL33 AZ100LVEL33 Datasheet (PDF) |
| File Size | 153.83 KB |
| Manufacturer | Arizona Microtek |
| Description | ECL/PECL / 4 Divider |
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The AZ10/100LVEL33 is an integrated ÷4 divider. The RESET pin is asynchronous and clears the output (Q Low, Q ¯ High) on the rising edge. Upon power-up, the internal flip-flop will be in a random logic state.
See all Arizona Microtek datasheets
| Part Number | Description |
|---|---|
| AZ10LVEL32 | ECL/PECL / 2 Divider |
| AZ10LVEL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ10LVEL16 | ECL/PECL Differential Receiver |
| AZ10LVEL16VS | ECL/PECL Differential Receiver |
| AZ10LVE111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ10LVE111 | ECL/PECL 1:9 Differential Clock Driver |
| AZ10LVE111E | ECL/PECL 1:9 Differential Clock Driver |
| AZ10LVE111E | ECL/PECL 1:9 Differential Clock Driver |
| AZ100E116 | ECL/PECL Quint Differential Line Receiver |
| AZ100E131 | ECL/PECL 4-bit D Flip-Flop |
