The AZ10/100EL32 is an integrated ÷2 divider.
The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of multiple EL32’s in a system.
| Part number | AZ100EL32 |
|---|---|
| Manufacturer | Arizona |
| File Size | 130.18 KB |
| Description | ECL/PECL / 2 Divider |
| Datasheet |
 AZ100EL32 Datasheet
|
|
|
| Part Number | Description | Manufacturer |
|---|---|---|
| AZ100EL01 | ECL/PECL 4-Input OR/NOR | Arizona Microtek |
| AZ100EL16 | ECL/PECL Differential Receiver | Arizona Microtek |
| AZ100EL16VO | ECL/PECL Oscillator Gain Stage and Buffer | AZM |
| AZ100EL58 | ECL/PECL 2:1 Multiplexer | Arizona Microtek |
| AZ100ELT22 | CMOS/TTL to Differential PECL Translator | Arizona Microtek |
| Part Number | Description |
|---|---|
| AZ100EL31 | ECL/PECL D Flip-Flop |
| AZ100EL07 | ECL/PECL 2-Input XOR/XNOR |
| AZ100EL11 | ECL/PECL 1:2 Differential Fanout Buffer |
| AZ100EL16VS | ECL/PECL Differential Receiver |
| AZ100ELT20 | CMOS/TTL to Differential PECL Translator |
The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.
