Arizona AZ100ELT21
The AZ100ELT21 is a differential PECL to CMOS/TTL translator. The small outline 8-lead packaging and the single gate of the ELT21 makes it ideal for those applications where space, performance and low power are at a premium. The ELT21 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device.| Part No. | AZ100ELT21 |
|---|---|
| Datasheet | AZ100ELT21 Download |
| Manufacturer | Arizona |
| Description | Differential PECL to CMOS/TTL Translator |
| Buy | Stock & Price |
FEATURES
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● 3.5ns Typical Propagation Delay Differential PECL Inputs CMOS/TTL Outputs Flow Through Pinouts Operating Range of 3.0V to 5.5V Direct Replacement for ON Semiconductor MC100ELT21 Use AZ100ELT21 for 10K
APPLICATIONS
PACKAGE SOIC 8 SOIC 8 T&R SOIC 8 T&R TSSOP 8 TSSOP 8 T&R TSSOP 8 T&R PART NO. AZ100ELT21D AZ100ELT21DR1 AZ100ELT21DR2 AZ100ELT21T AZ100ELT21TR1 AZ100ELT21TR2 MARKING AZM100ELT21 AZM100ELT21 AZM100ELT21 AZHLT21 AZHLT21 AZHLT21DESCRIPTION
Because PECL (Positive ECL) levels are used, only VCC and ground are required. For single-ended input applications, the VBB reference should be connected to one side of the D0/D0 ¯¯ differential input pair. The input signal is then fed to the other D0/D0 ¯¯ input. The VBB pin should be used only as a bias for the ELT21 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01µF capacitor. NOTE: Specification in ECL/PECL tables are valid when thermal equilibrium is established.
