D13x Datasheet | ArtInChip

Features | 6 .artinchip. 2. Functional Features - CPU Core ◦ E907 single-core processor, RV32IMAFDCP instruction set, 480 MHz@1.1V ◦ 32-KB L1 instruction cache and 32 KB L1 data cache ◦ Single/ double-precision floating-point unit (FPU), integrated with DSP instruction set ◦ Physical Memory Protection ◦ Standard CLINT and PLIC interrupt controllers ◦ Machine and User Mode ◦ Standard 2-wire JTAG debug interface - Boot ◦ Default boot sequence: SD Card(SDMC1) → SPI NOR → SPI NAND →e MMC(SDMC0) ◦ Default boot device configuration available by burning e Fuse - System Safety ◦ Secure boot by digital signatures ◦ Crypto Engine (CE) with support for AES/ TDES/ RSA and SHA/ HMAC ◦ SPI NAND/SPI NOR decode algorithms for SPI ENC ◦ The built-in e Fuse one-time programmable memory has 2048 bits, of which 512 bits are available for customer customization. It has an independent CHIPID and supports CE security key functions such as SSK/HUK/PNK/PSK0/ PSK1/PSK2/PSK3. It also supports setting read and write prohibitions. ◦ Embedded 256-bit TRNG - On-chip Memory ◦ 64 -KB BROM ◦ 1-MB SRAM, of which 256 KB can be configured for TCM ◦ PSRAM has the following specification choices: - 128 Mb DDR, with a 16-bit bus width and a maximum frequency of 200 MHz - 64 Mb DDR, with a 16-bit bus width and a maximum frequency of 200 MHz - 32 Mb, 8-bit width, with up to 200MHz DDR ◦ Spread spectrum supported for PSRAM clock - Memory Interfaces ◦ SPI NAND Flash / SPI NOR Flash supported for QSPI - Standard, dual SPI and quad SPI supported - Up to 100-MHz SDR for IO ◦ Two sets of e MMC 4.41/ SD 3.01/ SDIO 3.0 - 4-bit SDR25/ SDR50/ DDR50 data...