AK93C41A Datasheet | Asahi Kasei Microdevices

Features † ADVANCED CMOS EEPROM TECHNOLOGY † LOW VCC OPERATION … Vcc = 0.9V ∼ 3.6V † AK93C41A - - 1024 bits, 64 × 16 organization AK93C51A - - 2048 bits, 128 × 16 organization † SERIAL INTERFACE - Interfaces with popular microcontrollers and standard microprocessors † LOW POWER CONSUMPTION - 10µA Max. Standby (VCC=3.6V) † Automatic address increment (READ) † Automatic write cycle time-out with auto-ERASE † Busy/Ready status signal † Software controlled write protection † Hardware write protect for lower block (AK93C51A only) † IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package Preliminary Block Diagram DAM05E-01 -1- 1999/12 ASAHI KASEI [AK93C41A/51A] General Description The AK93C41A/51A is a 1024/2048-bit serial CMOS EEPROM divided into 64/128 registers of 16 bits each. The AK93C41A/51A has 4 instructions such as READ, WRITE, EWEN and EWDS. Those instructions control the AK93C41A/51A. The AK93C41A/51A can operate full function under wide operating voltage range from 0.9V to 3.6V. The charge up circuit is integrated for high voltage generation that is used for write operation. A serial interface of AK93C41A/51A, consisting of chip select (CS), serial clock (SK), data-in (DI) and dataout (DO), can easily be controlled by popular microcontrollers or standard microprocessors. AK93C41A/51A takes in the write data from data input pin (DI) to a register synchronously with rising edge of input pulse of serial clock pin (SK). And at read operation, AK93C41A/51A takes out the read data from a register to data output pin (DO) synchronously with rising edge of SK. The DO pin is usually in high impedance state. The DO pin outputs "L" or "H" in case of data output or Busy/Ready signal output. Software and Hardware controlled write protection When Vcc is applied to the part, the part automatically powers up in the ERASE/WRITE Disable state. In the ERASE/WRITE disable state, execution of WRITE instruction is disabled. Before WRITE instruction is...