FEATURES
● High-performance Fully CMOS, Electrically-erasable Complex Programmable Logic Device – 32 Macrocells – 5 Product Terms per Macrocell, Expandable up to 40 per Macrocell – 44 Pins – 5.0 ns Pin-to-pin Propagation Delay – Registered Operation up to 333 MHz – Enhanced Routing Resources – Optimized for 1.8V Operation – 2 I/O Banks to Facilitate Multi-voltage I/O Operation: 1.8V, 2.5V, 3.3V In-System Programming (ISP) Supported – 1.8V ISP Using IEEE 1532 (JTAG) Interface – Boundary-scan Testing to IEEE JTAG Std. 1149.1 Supported Flexible Logic Macrocell – D/Latch Configurable Flip-flops – Global and Individual Register Control Signals – Global and Individual Output Enable – Programmable Output Slew Rate with Low Output Drive – Programmable Open Collector Output Option – Maximum Logic Utilization by Burying a Register with a COM Output and Vice Versa Fully Green (RoHS Compliant) 10 µA Static Current Power Saving Option During Operation Using PD1, PD2 Pins Programmable Pin-keeper Opt...
Atmel
