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T89C51CC01 - Enhanced 8-Bit Microcontroller

General Description

The T89C51CC01 is the first member of the CANaryTM family of 8-bit microcontrollers dedicated to CAN network applications.

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Key Features

  • 80C51 Core Architecture.
  • 256 Bytes of On-chip RAM.
  • 1K Bytes of On-chip XRAM.
  • 32K Bytes of On-chip Flash Memory.
  • Data Retention: 10 Years at 85°C Erase/Write Cycle: 100K.
  • Boot Code Section with Independent Lock Bits.
  • 2K Bytes of On-chip Flash for Bootloader.
  • In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability.
  • 2K Bytes of On-chip EEPROM Erase/Write Cycle: 100K.
  • 14-sources 4-level In.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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Features • 80C51 Core Architecture • 256 Bytes of On-chip RAM • 1K Bytes of On-chip XRAM • 32K Bytes of On-chip Flash Memory – Data Retention: 10 Years at 85°C Erase/Write Cycle: 100K • Boot Code Section with Independent Lock Bits • 2K Bytes of On-chip Flash for Bootloader • In-System Programming by On-Chip Boot Program (CAN, UART) and IAP Capability • 2K Bytes of On-chip EEPROM Erase/Write Cycle: 100K • 14-sources 4-level Interrupts • Three 16-bit Timers/Counters • Full Duplex UART Compatible 80C51 • Maximum Crystal Frequency 40 MHz, in X2 Mode, 20 MHz (CPU Core, 20 MHz) • Five Ports: 32 + 2 Digital I/O Lines • Five-channel 16-bit PCA with: – PWM (8-bit) – High-speed Output – Timer and Edge Capture • Double Data Pointer • 21-bit Watchdog Timer (7 Programmable Bits) • A 10-bit Resolution A