Atmel TS81102G0
The TS81102G0 is a monolithic 10-bit high-speed (up to 2 GHz) demultiplexor, designed to run with all kinds of ADCs and more specifically with Atmel’s high-speed ADC 8-bit 1 Gsps TS8388B and ADC 10-bit 2 Gsps TS83102G0B. The TS81102G0 uses an innovative architecture, including a sampling delay adjust and tunable output levels. It allows users to process the high-speed output data stream down to processor speed and uses the very high-speed bipolar technology (25 GHz NPN cut-off frequency).| Part No. | TS81102G0 |
|---|---|
| Datasheet | TS81102G0 Download |
| Manufacturer |  Atmel |
| Description | Monolithic 10-bit high-speed (up to 2 GHz) demultiplexor |
| Buy | Stock & Price |
FEATURES
● Programmable DMUX Ratio: – 1:4: Data Rate Max = 1 Gsps – PD (8b/10b) < 4.3/4.7 W (ECL 50Ω output) – 1:8: Data Rate Max = 2 Gsps – PD (8b/10b) < 6/6.9 W (ECL 50Ω output) – 1:16 with 1 TS8388B or 1 TS83102G0B and 2 DMUX● Parallel Output Mode
● 8-/10-bit
● ECL Differential Input Data
● DataReady or DataReady/2 Input Clock
● Input Clock Sampling Delay Adjust
● Single-ended Output Data: – Adjustable Common Mode and Swing – Logic Threshold Reference Output – (ECL, PECL, TTL)
● Asynchronous Reset
● Synchronous Reset
● ADC + DMUX Multi-channel
APPLICATIONS
: – Stand-alone Delay Adjust Cell for ADCs Sampling Instant Alignment● Differential Data Ready Output
● Built-in Self Test (BIST)
● Dual Power Supply VEE = -5V, VCC = +5V
● Radiation Tolerance Oriented Design (More than 100 Krad (Si) Expected)
● TBGA 240 (Cavity Down) Package DMUX 8-/10-bit 2 GHz 1:4/8 TS81102G0
DESCRIPTION
Rev. 2105C–BDC–11/03 1 Block Diagram Figure 1. Block Diagram Data Path Clock Path SwiAdj VplusDOut VCC GND...
