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AS4DDR232M64PBG - 32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

Datasheet Summary

Description

On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits DNU BA0, BA1 DQx Future Input Input Bank Address inputs Input/Output Data bidirectional input/Output pins Vref VCC Supply Supply SSTL_18 Voltage Reference Core Power Supply V

Features

  • DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package:.
  • 255 Plastic Ball Grid Array (PBGA), 25 x 32mm.
  • 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ.

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Datasheet Details

Part number AS4DDR232M64PBG
Manufacturer Austin Semiconductor
File Size 416.40 KB
Description 32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit
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Full PDF Text Transcription

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i PEM 2.1 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR232M64PBG 32Mx64 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Military Temp Package: • 255 Plastic Ball Grid Array (PBGA), 25 x 32mm • 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Four internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.
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