AS4DDR232M72PBG Datasheet PDF

FEATURES

„ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package:
● 255 Plastic Ball Grid Array (PBGA), 25 x 32mm
● 1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Four internal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.1V power supply and I/O (VCC/VCCQ) Programmable CAS latency: 3, 4, 5, or 6 Posted CAS additive latency: 0, 1, 2, 3 or 4 Write latency = Read latency - 1* tCK Organized as 32M x 72 w/ support for x80 Weight: AS4DDR232M72PBG ~ 3.5 grams typical BENEFITS „ „ „ „ „ „ SPACE conscious PBGA defined for easy SMT manufacturability (50 mil ball pitch) Reduced part count 47% I/O reduction vs Individual CSP appr...