AS4DDR232M72PBG - 32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit

Product Overview

Austin Semiconductor

Datasheet Details

Part number	AS4DDR232M72PBG
Manufacturer	Austin Semiconductor
File Size	290.32 KB
Description	32Mx72 DDR2 SDRAM iNTEGRATED Plastic Encapsulated Microcircuit
Datasheet	AS4DDR232M72PBG Datasheet
Additional preview pages of the AS4DDR232M72PBG datasheet.

Product details

Description

On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits A7, A8, A9, A10, B7, Ax Input B8, B9, B10, C7, C8, C9, C10, D7 D8, D9, D10 DNU Future Input E8, E9 BA0, BA1 Input A2, A3, A4, A13, A14, DQx Input/Output A15, B1, B2, B3, B4, B13, B14, B15, B16, C1, C2, C3, C4, C13, C14, C15, C16, D1, D2, D3, D4, D13, D14, D15, D16, E1, E16, M1, M16, N1, N2, N3, N4, N7, N8, N9, N10, N13, N14, N15, N16, PP1, P2, P3, P4, P7, P8, P9, P10, P13, P14

Features

DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package:.
255 Plastic Ball Grid Array (PBGA), 25 x 32mm.
1.27mm pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4-bit prefetch architecture DLL for alignment of DQ.

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Published: Sep 26, 2009 |