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AS4DDR264M65PBG1 - 64Mx64 DDR2 SDRAM w/ DUAL CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit

Description

On-Die-Termination: Registered High enables on data bus termination Differential input clocks, one set for each x16bits Clock enable which activates all on silicon clocking circuitry Chip Selects, one for each 16 bits of the data bus width Command input which along with CAS, WE and CS define operati

Features

  • DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package:.
  • Proprietary Enchanced Die Stacked iPEM.
  • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm.
  • 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SD.

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Datasheet Details

Part number AS4DDR264M65PBG1
Manufacturer Austin Semiconductor
File Size 295.81 KB
Description 64Mx64 DDR2 SDRAM w/ DUAL CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit
Datasheet download datasheet AS4DDR264M65PBG1 Datasheet
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Full PDF Text Transcription

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i PEM 4.2 G b SDRAM-DDR2 Gb Austin Semiconductor, Inc. AS4DDR264M65PBG1 64Mx64 DDR2 SDRAM w/ DUAL CONTROL BUS iNTEGRATED Plastic Encapsulated Microcircuit FEATURES „ „ „ DDR2 Data rate = 667, 533, 400 Available in Industrial, Enhanced and Extended Temp Package: • Proprietary Enchanced Die Stacked iPEM • 208 Plastic Ball Grid Array (PBGA), 16 x 23mm • 1.00mm ball pitch Differential data strobe (DQS, DQS#) per byte Internal, pipelined, double data rate architecture 4n-bit prefetch architecture DLL for alignment of DQ and DQS transitions with clock signal Eightinternal banks for concurrent operation (Per DDR2 SDRAM Die) Programmable Burst lengths: 4 or 8 Auto Refresh and Self Refresh Modes (I/T Version) On Die Termination (ODT) Adjustable data – output drive strength 1.8V ±0.
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