Austin Semiconductor AS4LC4M16
The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V. The device is functionally organized as 4,194,304 locations containing 16 bits each.| Part No. | AS4LC4M16 |
|---|---|
| Datasheet | AS4LC4M16 Download |
| Manufacturer |  Austin Semiconductor |
| Description | 4 MEG x 16 DRAM |
| Buy | Stock & Price |
FEATURES
● Single +3.3V ±0.3V power supply.● Industry-standard x16 pinout, timing, functions, and package.
● 12 row, 10 column addresses
● High-performance CMOS silicon-gate process
● All inputs, outputs and clocks are LVTTL-compatible
● Extended Data-Out (EDO) PAGE MODE access
● 4,096-cycle CAS\-BEFORE-RAS\ (CBR) REFRESH distributed across 64ms
● Optional self refresh (S) for low-power data retention
● Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020 AS4LC4M16 PIN ASSIGNMENT (Top View) 50-Pin TSOP (DG) OPTIONS
● Package(s) 50-pin TSOP (400-mil)
● Timing 50ns access 60ns access
● Refresh Rates Standard Refresh Self Refresh
● Operating Temperature Ranges Military (-55°C to +125°C) Industrial (-40°C to +85°C) MARKINGS DG -5 -6 Configuration Refresh Row Address Column Addressing 4 Meg x 16 4K A0-A11 A0-A9 None S* XT IT NOTE: The \ symbol indicates signal is active LOW. *Contact factory for availability. Self refresh option available on IT version only. KEY TIMING PARAMETERS tRAC SPEE...
