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AS4LC4M16 - 4 MEG x 16 DRAM

Description

The 4 Meg x 16 DRAM is a high-speed CMOS, dynamic random-access memory device containing 67,108,864 bits and designed to operate from 3V to 3.6V.

The device is functionally organized as 4,194,304 locations containing 16 bits each.

Features

  • Single +3.3V ±0.3V power supply.
  • Industry-standard x16 pinout, timing, functions, and package.
  • 12 row, 10 column addresses.
  • High-performance CMOS silicon-gate process.
  • All inputs, outputs and clocks are LVTTL-compatible.
  • Extended Data-Out (EDO) PAGE MODE access.
  • 4,096-cycle CAS-BEFORE-RAS (CBR).

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Datasheet preview – AS4LC4M16

Datasheet Details

Part number AS4LC4M16
Manufacturer Austin Semiconductor
File Size 545.57 KB
Description 4 MEG x 16 DRAM
Datasheet download datasheet AS4LC4M16 Datasheet
Additional preview pages of the AS4LC4M16 datasheet.

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DRAM Austin Semiconductor, Inc. 4 MEG x 16 DRAM Extended Data Out (EDO) DRAM FEATURES • Single +3.3V ±0.3V power supply. • Industry-standard x16 pinout, timing, functions, and package. • 12 row, 10 column addresses • High-performance CMOS silicon-gate process • All inputs, outputs and clocks are LVTTL-compatible • Extended Data-Out (EDO) PAGE MODE access • 4,096-cycle CAS-BEFORE-RAS (CBR) REFRESH distributed across 64ms • Optional self refresh (S) for low-power data retention • Level 1 Moisture Sensitivity Rating, JEDEC J-STD-020 AS4LC4M16 PIN ASSIGNMENT (Top View) 50-Pin TSOP (DG) OPTIONS • Package(s) 50-pin TSOP (400-mil) www.DataSheet4U.
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