AS5C4008 Datasheet | Austin Semiconductor

FEATURES - - - - - - High Speed: 17, 20, 25, 35 and 45ns High-performance, low power military grade device Single +5V ±10% power supply Easy memory expansion with CE and OE options All inputs and outputs are TTL-patible Ease of upgradability from 1 Meg using the 32 pin evolutionary version. OPTIONS - Timing 15ns access (contact factory) 17ns access 20ns access 25ns access 35ns access .. 45ns access - Operating Temperature Range Military: -55o C to +125o C Industrial: -40o C to +85o C - Packages Ceramic Dip (600 mil) Ceramic Flatpack Ceramic LCC Ceramic SOJ Ceramic LCC (contact factory) - Options 2V data retention/ low power MARKING -15 -17 -20 -25 -35 -45 XT IT CW F EC ECJ ECA L No. 112 No. 304 No. 209 No. 502 No. 208 32-Pin Flat Pack (F) A18 A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 I/O1 I/O2 Vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 Vcc A15 A17 WE A13 A8 A9 A11 OE A10 CE I/O7 I/O6 I/O5 I/O4 I/O3 GENERAL DESCRIPTION The AS5C4008 is a 4 megabit monolithic CMOS SRAM, organized as a 512K x 8. The evolutionary 32 pin device allows for easy upgrades from the 1 meg SRAM. For flexibility in high-speed memory applications, ASI offers chip enable (CE) and output enable (OE) capabilities. These enhancements can place the outputs in High-Z for additional flexibility in system design. Writing to these devices is acplished when write enable (WE) and CE inputs are both LOW. Reading is acplished when WE remains HIGH and CE and OE go LOW. This allows systems designers to meet low standby power requirements. All devices operate from a single +5V power supply and all inputs are fully TTL-patible. AS5C4008 Rev. 5.5 12/01 A7 A6 A5 A4 A3 A2 A1 A0 I/O0 4 3 2 32 31 30 5 29 1 6 28 7 27 8 26 9 25 10 24 11 23 12 22 13 21 14 15 16 17 18 19 20 I/O6 I/O5 I/O4 I/O3 Vss I/O2 I/O1 A12 A14 A16 A18 Vcc A15 A17 NOTE: Not all binations of operating temperature, speed, data retention and low power are necessarily available. Please contact factory...