AS5C4009LL Description
The AS5C4009LL is organized as 524,288 x 8 SRAM utilizing a special ultra low power design process. ASI’s pinout adheres to the JEDEC standard for pinout on 4 megabit SRAMs. The evolutionary 32 pin version allows for easy upgrades from the 1 meg SRAM design.
AS5C4009LL Key Features
- Ultra Low Power with 2V Data Retention (0.2mW MAX worst case Power-down standby)
- Fully Static, No Clocks
- Single +5V ±10% power supply
- Easy memory expansion with CE and OE options
- All inputs and outputs are TTL-patible
- Three state outputs
- Timing 55ns access 70ns access 85ns access 100ns access
- Packages Ceramic Dip (600 mil) Ceramic SOJ5 Plastic TSOP