AS5SS128K36 Description
The Austin Semiconductor, Inc. Zero Bus Latency SRAM family employs high-speed, low-power CMOS designs using an advanced CMOS process. ASI’s 4Mb ZBL SRAMs integrate a 128K x 36 SRAM core with advanced synchronous peripheral circuitry and a 2-bit burst counter.
AS5SS128K36 Key Features
- High frequency and 100% bus utilization
- Fast cycle times: 11ns & 12ns
- Single +3.3V +5% power supply (VDD)
- Advanced control logic for minimum control signal interface
- Individual BYTE WRITE controls may be tied LOW
- Single R/W (READ/WRITE) control pin
- CKE pin to enable clock and suspend operations
- Three chip enables for simple depth expansion
- Clock-controlled and registered addresses, data I/Os and control signals
- Internally self-timed, fully coherent WRITE