AS5SS256K36 Datasheet | Austin Semiconductor

FEATURES ! ! ! ! ! ! ! AS5SS256K36 & AS5SS256K36A PIN ASSIGNMENT (Top View) SSRAM ! ! ! ! ! ! Organized 256K x 36 Fast Clock and OE access times Single +3.3V +0.3V/-0.165V power supply (VDD) SNOOZE MODE for reduced-power standby mon data inputs and data outputs Individual BYTE WRITE control and GLOBAL WRITE Three chip enables for simple depth expansion and address pipelining Clock-controlled and registered addresses, data I/Os and control signals Internally self-timed WRITE cycle Burst control (interleaved or linear burst) Automatic power-down for portable applications 100-lead TQFP package for high density, high speed Low capacitive bus loading 100-pin TQFP (DQ) (2-chip enable version, “A” indicator) SA SA ADV ADSP ADSC OE BWE GW CLK Vss VDD SA BWa BWb BWc BWd CE2 CE SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 OPTIONS .. MARKING -8.5- -10 DQ No. 1001 A (PRELIMINARY) no indicator XT- IT Timing 8.5ns/10ns/100MHz 10ns/15ns/66MHz ! Packages 100-pin TQFP (2-chip enable) ! Pinout 2-chip Enables 3-chip Enables ! Operating Temperature Ranges Military (-55o C to +125o C) Industrial (-40o C to +85o C) ! DQPc DQc DQc VDDQ Vss DQc DQc DQc DQc Vss VDDQ DQc DQc Vss VDD NC Vss DQd DQd VDDQ Vss DQd DQd DQd DQd Vss VDDQ DQd DQd DQPd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 DQPb DQb DQb V DDQ Vss DQb DQb DQb DQb Vss V DDQ DQb DQb Vss NC V DD ZZ DQa DQa V DDQ Vss DQa DQa DQa DQa Vss VDDQ DQa DQa DQPa 100-pin TQFP (DQ) (3-chip enable version, no indicator) SA SA ADV ADSP ADSC OE BWE GW CLK Vss VDD CE2 BWa BWb BWc BWd CE2 CE SA SA 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 SA SA SA SA SA SA SA NF NF VDD Vss DNU DNU SA0 SA1 SA SA SA SA MODE - NOTE: -8.5/XT bination not available. GENERAL DESCRIPTION The AS5SS256K36 employs high-speed, low-power...