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MT4C1004J883C - 4 MEG x 1 DRAM FAST PAGE MODE

General Description

The MT4C1004J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x1 configuration.

During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time.

Key Features

  • Industry standard x1 pinout, timing, functions and packages.
  • High-performance, CMOS silicon-gate process.
  • Single +5V ± 10% power supply.
  • Low-power, 2.5mW standby; 300mW active, typical.
  • All inputs, outputs and clocks are fully TTL and CMOS compatible.
  • 1,024-cycle refresh distributed across 16ms.
  • Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR), and HIDDEN.
  • FAST PAGE MODE access cycle www. DataSheet4U. com.
  • CBR.

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Datasheet Details

Part number MT4C1004J883C
Manufacturer Austin Semiconductor
File Size 146.79 KB
Description 4 MEG x 1 DRAM FAST PAGE MODE
Datasheet download datasheet MT4C1004J883C Datasheet

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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AUSTIN SEMICONDUCTOR, INC. MT4C1004J MT5C1005 883C 4 MEG 256K x x1 4 DRAM SRAM DRAM AVAILABLE AS MILITARY SPECIFICATONS • SMD 5962-90622 • MIL-STD-883 4 MEG x 1 DRAM FAST PAGE MODE PIN ASSIGNMENT (Top View) 18-Pin DIP D WE RAS *A10 A0 A1 A2 A3 Vcc 1 2 3 4 5 6 7 8 9 18 17 16 15 14 13 12 11 10 Vss Q CAS A9 A8 A7 A6 A5 A4 20-Pin ZIP A9 Q D RAS NC A0 A2 Vcc A5 A7 1 3 5 7 9 11 13 15 17 19 FEATURES • Industry standard x1 pinout, timing, functions and packages • High-performance, CMOS silicon-gate process • Single +5V ± 10% power supply • Low-power, 2.