MT4C1004J883C Overview
The MT4C1004J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x1 configuration. During READ or WRITE cycles, each bit is uniquely addressed through the 22 address bits which are entered 11 bits (A0 -A10) at a time. /R/A/S is used to latch the first 11 bits and /C/A/S the latter 11 bits.
MT4C1004J883C Key Features
- Industry standard x1 pinout, timing, functions and packages
- High-performance, CMOS silicon-gate process
- Single +5V ± 10% power supply
- Low-power, 2.5mW standby; 300mW active, typical
- All inputs, outputs and clocks are fully TTL and CMOS patible
- 1,024-cycle refresh distributed across 16ms
- Refresh modes: /R?A/S-ONLY, /C/A/S-BEFORE-/R/?A/S (CBR), and HIDDEN
- FAST PAGE MODE access cycle
- CBR with ?W/E a HIGH (JEDEC test mode capable via WCBR)
- Timing 70ns access 80ns access 100ns access 120ns access