MT4C4001J Overview
The MT4C4001J is a randomly accessed solid-state memory containing 4,194,304 bits organized in a x4 configuration. During READ or WRITE cycles each bit is uniquely addressed through the 20 address bits which are entered 10 bits (A0-A9) at a time. RAS is used to latch the first 10 bits and CAS the later 10 bits.
MT4C4001J Key Features
- Industry standard x4 pinout, timing, functions, and packages
- High-performance, CMOS silicon-gate process
- Single +5V±10% power supply
- Low-power, 2.5mW standby; 300mW active, typical
- All inputs, outputs, and clocks are fully TTL and CMOS patible
- 1,024-cycle refresh distributed across 16ms
- Refresh modes: RAS-ONLY, CAS-BEFORE-RAS (CBR), and HIDDEN
- FAST PAGE MODE access cycle
- CBR with WE a HIGH (JEDEC test mode capable via WCBR)
- Timing 70ns access 80ns access 100ns access 120ns access
