SM55161A Datasheet | Austin Semiconductor

FEATURES - Organization: - DRAM: 262 144 by 16 Bits - SAM: 512 by 16 Bits - Dual-Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports - Bidirectional Data-Transfer Function From the DRAM to the Serial-Data Register, and from Serial Data Register to DRAM - (8 x 8) x 2 Block Write feature for fast area fill - Write-Per-Bit Feature for Selective Write to Each RAM I/O; Two Write-Per-Bit Modes to Simplify System Design - Byte-Write Control (CASL, CASU) Provides Flexibility - Extended Data Output for Faster System Cycle Time - Enhanced Page-Mode Operation for Faster Access - CAS-Before-RAS (CBR) and Hidden-Refresh Modes - Long Refresh Period: Every 8 ms (Maximum) - Up to 50-MHz Uninterrupted Serial-Data Streams - 512 Selectable Serial-Register Starting Locations - SE-Controlled Register-Status QSF - Split-Register-Transfer Read for Simplified Real-Time Register Load - Programmable Split-Register Stop Point - 3-State Serial Outputs Allow Easy Multiplexing of Video-Data Streams - Pin-out patible upgrade from SM55161 - patible With JEDEC Standards PIN DESCRIPTIONS PIN A0-A8 CASL, CASU DQ0-DQ15 DSF NC/GND DESCRIPTION Address inputs Column-Address Strobe/Byte Selects DRAM Data I/O, Write Mask Data Special Function Select Special-Function Select No Connect/Ground (NOTE: Not connected internally to VSS) Special-Function Output Row-Address Strobe Serial Clock Serial Enable Serial-Data Output Output Enable, Transfer Select 5V Supply (TYP) Ground DRAM Write-Enable Select OPTIONS - Timing 70ns access 75ns access 80ns access - Package 68 pin PGA 64 pin Flatpack - Operating Temperature Ranges - Military (-55o C to +125o C) .. - Industrial (-40o C to +85o C) MARKING -70 -75 -80 QSF RAS SC SE SQ0-SQ15 TRG VCC GB HKC VSS WE M suffix I suffix For more products and information please visit our web site at .austinsemiconductor. Austin Semiconductor, Inc. reserves the right to change products or specifications without notice. SMJ55161A Rev. 1.6...