Overview: Bt261
30 MHz Pixel Clock Monolithic CMOS HSYNC Line Lock Controller
The Bt261 HSYNC Line Lock Controller is designed specifically for image capture applications. Either posite video or TTL posite sync information is input via VIDEO. An internal sync separator separates horizontal and vertical sync information. Programmable horizontal and vertical video timing enables recovery of both standard and nonstandard timing information. An external VCO may be used in conjunction with the on-chip phase parator for implementation of clocks locked to the horizontal frequency. Alternately, a high-speed clock (OSC) may be divided down to generate the pixel clock. The phase of the generated pixel clock is adjusted to align with the noise-gated CSYNC. The higher the OSC clock rate, the lower the pixel clock jitter (the maximum being one half the OSC clock period). The OSC inputs may be configured to be either TTL or ECL patible. Thus, four TTL clocks, two TTL clocks and one differential ECL clock, or two differential ECL clocks may be used. The ECL clock inputs are designed to be driven by 10KH ECL using a single +5 V supply. The CLAMP and ZERO outputs are programmed by the MPU to DC restore the video signal and to zero the Image Digitizer or A/D converter at the appropriate time.
