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ADS5240 - 40MSPS ADC

Download the ADS5240 datasheet PDF. This datasheet also covers the ADS5240_Burr variant, as both devices belong to the same 40msps adc family and are provided as variant models within a single manufacturer datasheet.

General Description

The ADS5240 is a high-performance, 4-channel, 40MSPS analog-to-digital converter (ADC).

Internal references are provided, simplifying system design requirements.

Low power consumption allows for the highest of system integration densities.

Key Features

  • Maximum Sample Rate: 40MSPS 12-Bit Resolution No Missing Codes Power Dissipation: 607mW CMOS Technology Simultaneous Sample-and-Hold 70.5dBFS SNR at 10MHz IF Internal and External References 3.3V Digital/Analog Supply Serialized LVDS Outputs Integrated Frame and Bit Patterns MSB and LSB First Modes Option to.

📥 Download Datasheet

Note: The manufacturer provides a single datasheet file (ADS5240_Burr-BrownCorporation.pdf) that lists specifications for multiple related part numbers.

📁 Similar Datasheet

Part Number Description Manufacturer
ADS5240 Analog-to-Digital Converters Texas Instruments
ADS5231 Analog-to-Digital Converter Burr-Brown
ADS5232 Analog-to-Digital Converter Burr-Brown
ADS5237 Analog-to-Digital Converter Burr-Brown
ADS5263 100-MSPS High-SNR ADC Texas Instruments

Other Datasheets by Burr-Brown (Texas Instruments)

Part Number Description
ADS5242 65MSPS Analog-to-Digital Converter
ADS5220 ANALOG-TO-DIGITAL CONVERTER
ADS5221 ANALOG-TO-DIGITAL CONVERTER
ADS5270 8-Channel 12-Bit 40MSPS ADC
ADS5271 50MSPS ADC

Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

View original datasheet text
BurrĆBrown Products from Texas Instruments ADS5240 ¨ SBAS326C – JUNE 2004 – REVISED DECEMBER 2004 4-Channel, 12-Bit, 40MSPS ADC with Serial LVDS Interface FEATURES • • • • • • • • • • • • • • • • • • • Maximum Sample Rate: 40MSPS 12-Bit Resolution No Missing Codes Power Dissipation: 607mW CMOS Technology Simultaneous Sample-and-Hold 70.5dBFS SNR at 10MHz IF Internal and External References 3.3V Digital/Analog Supply Serialized LVDS Outputs Integrated Frame and Bit Patterns MSB and LSB First Modes Option to Double LVDS Clock Output Currents Pin- and Format-Compatible Family HTQFP-64 PowerPAD™ Package An integrated phase lock loop multiplies the incoming ADC sampling clock by a factor of 12. This 12x clock is used in the process of serializing the data output from each channel.