ADS852 Datasheet | Burr-Brown

.Data Sheet.co.kr ® PRELIMINARY INFORMATION SUBJECT TO CHANGE WITHOUT NOTICE 14-Bit, 65MHz Sampling ANALOG-TO-DIGITAL CONVERTER Features q HIGH DYNAMIC RANGE: High SFDR: 100d B at 20MHz f IN High SNR: 75d B at 20MHz f IN q PREMIUM TRACK/HOLD: High Bandwidth: 1GHz Low Jitter: 0.25p S rms Differential or Single-Ended Inputs Selectable Full-Scale Input Range q FLEXIBLE CLOCKING: Differential or Single-Ended Accepts Sine or Square Wave Clocking Down to 0.5Vp-p Variable Threshold Level APPLICATIONS q BASESTATION WIDEBAND RADIOS: CDMA, GSM, TDMA, 3G, AMPS, NMT q TEST INSTRUMENTATION q CCD IMAGING differential operation gives the lowest even-order harmonic ponents. A lower input voltage of 3Vp-p or 2Vp-p can also be selected using the internal references, further optimizing SFDR. Alternatively, a single-ended input range can be used by tying the IN input to the mon-mode voltage if desired. The ADS852 also provides an over-range flag that indicates when the input signal has exceeded the converter’s full-scale range. This flag can also be used to reduce the gain of the front end signal conditioning circuitry. It also employs digital error correction techniques to provide excellent differential linearity for demanding imaging applications. The ADS852 is available in a small 48-lead TQFP package. DESCRIPTION The ADS852 is a high-dynamic range 14-bit, 65MHz pipelined analog-to-digital converter. It includes a highbandwidth linear track/hold that gives excellent spurious performance up to and beyond the Nyquist rate. This highbandwidth track/hold also has a low jitter of only 0.25p S rms, leading to excellent SNR performance. The clock input can accept a low level differential sine wave or square wave signal down to 0.5Vp-p, further improving the SNR performance. It also accepts a single-ended clock signal and has flexible threshold levels. The ADS852 has a 4Vp-p differential input range (2Vp-p x 2 inputs, +16d Bm) for optimum signal-to-noise ratio....