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CP5004 Datasheet PDF

CHIP CP5004

The CP5004 is one of the ETLINK series chips designed by Chiphomer Technology Limited. It is a 4-channels short-haul PCM transceiver with reference clock of 2.048MHz (E1) or 1.544MHz (T1/J1), contains four independent receivers and four independent transmitters on a single chip.
Part No. CP5004
Datasheet CP5004 Download
Manufacturer
CHIP
Description Quad E1/T1 Line Interface Unit
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CP5004 datasheet page 1 preview

FEATURES

●Four channel E1/T1/J1 LIU
●3.3V supplies with 5V tolerant I/O
●Ultra low power consumption, 120mw per channel (typ.)
●Crystal-less jitter attenuator
●Constant throughput delay
●Meets ITU G.736, G.742, G.823 and ETSI CTR12/13 specification
●Optimized for SDH applications, meets ITU G.783 mapping jitter specification
●LOS detector meets ITU G.775, ANSI T1.231 and ETSI ETS 300 233
●Provides non-intrusive Protected Monitoring Points (PMP) per ITU G.772
●Transmits return loss exceeds ETSI ETS 300166
●Supports 100ohm T1, 110ohm J1, 75ohm E1 coaxial and 120ohm E1 twisted pair applications
●Programmable Waveform shaper
●AMI or HDB3/B8ZS encoder/decoder LQFP144 -40℃ to 85℃ MCLK SERIAL/PARALLEL PORT MODE,LOOP0~3,JASEL Hardware/Host Interface Clock Generator JTAG Interface JTAG Serial Channel 3 LOS RTIP3 RRING3 Analog Loopback Line Driver Pulse Shaper G.772 Protected Monitoring Point LOS3 RDP3 RDN3 RCLK3 Data Recovery Clock Recovery Digital Loopback JA on Receiver Remote Loopback JA on...
CP5004 page 2 preview