Datasheet Summary
CBM9002A OPERATION INSTRUCTION
Features
- Integrated, Industry Standard Enhanced 8051
- 48 MHz, 24 MHz, or 12 MHz CPU operation
- Four clocks per instruction cycle
- Two USARTS
- Three counter/timers
- Two data pointers
- Expanded interrupt system
- Vectored USB Interrupts and GPIF/FIFO Interrupts
- Storage
- 16 Kbytes of On-Chip Code/Data RAM
- 0.5 Kbytes of On-Chip dataRAM
- Clock, reset
- 3.3V Operation with 5V Tolerant Inputs
- Power on reset (POR), external RESET input
- 24MHz (± 100ppm) crystal oscillator
- Low Power
- It supports suspend mode, and the minimum power consumption is no more than 1mA
- ICC No More than 85 mA in any Mode
- USB
- Support standard USB2.0...