Full PDF Text Transcription for CVPD-925 (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
CVPD-925. For precise diagrams, and layout, please refer to the original PDF.
Ultra-Low Noise LVPECL VCXO CVPD-925 Model 9×14 mm SMD, 3.3V, LVPECL with -160 dBc/Hz Noise Floor! Frequency Range: Frequency Pulling: Temperature Range: (Option X) Stora...
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requency Range: Frequency Pulling: Temperature Range: (Option X) Storage: Input Voltage: Input Current: Output: Symmetry: Rise/Fall Time: Linearity: Logic: Disable Time: Start-up Time: Input: Modulation Bandwidth: Input Impedance: Control Voltage: Tuning Sensitivity: Sub-Harmonics: Phase Jitter: 12 kHz to 20 MHz Phase Noise: Aging: 131 MHz to 160 MHz ±20ppm APR Min 0°C to 70°C -40°C to 85°C -45°C to 90°C 3.3V ±0.3V 88mA Max Differential LVPECL 45/55% Max @ zero crossing point 1ns Max (20% to 80%) ±10% Max Terminated to Vcc-2V into 50 ohms "0" = Vcc-1.85V Min, Vcc-1.62V Max "1" = Vcc-1.02V Min, Vcc-0.81V Max 200ns 1ms Typic
CVPD-925 Datasheet
