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CL12464FF Datasheet PDF

CURIOUS CL12464FF

The CL12464FF receiver converts serial four LVDS data streams data back into parallel 28bits (24bits of RGB data and 4bits of HSYNC, VSYNC, DE and Control1) of LVCMOS parallel. The CL12464FF receiver’ outputs are Falling edge clock. The CL12464FF receiver is an ideal means to solve EMI and cable size problems associated with wide, high-speed LVCMOS interfaces.
Part No. CL12464FF
Datasheet CL12464FF Download
Manufacturer CURIOUS
Description LVDS Receiver 24bit FPD-link 85MHz
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CL12464FF datasheet page 1 preview

DESCRIPTION

Pin Name RxOUT RxIN+ RxINRxCLKOUT RxCLKIN+ RxCLKIN- Power Down Vcc / GND PLL Vcc / PLL GND LVDS Vcc / LVDS GND LVDS Receiver 24bit FPD-link 85MHz No of Pin 28 4 4 1 1 1 1 3/5 1/2 2/4 I/O OUT IN IN OUT IN IN IN IN IN IN Pin

DESCRIPTION

LVCMOS Data Outputs Positive LVDS Differential Data Inputs Negative LVDS Differential Data Inputs LVCMOS Level Clock Output Positive LVDS Differential Clock Input Negative LVDS Differential Clock Input H:Normal Operation L:Power Down (all Outputs are Hi-Z) Power Supply/Ground Pins for LVCMOS Outputs Power Supply/Ground Pins for PLL Power Supply/Ground Pins for LVDS Inputs Control Signal Truth Table Power Down 0 0 0 0 1 1 1 1 R_F 0 0 1 1 0 0 1 1 OE 0 1 0 1 0 1 0 1 RxOUT All Outputs Hi-Z All ”0” Outputs All Outputs Hi-Z All ”0” Outputs All Outputs Hi-Z All Data Outputs All Outputs Hi-Z All Data Outputs RxCLKOUT Output Hi-Z ”0” Output Output Hi-Z ”0” Output Output Hi-Z Falling Edge Output Hi-Z Rising Edge CURIOUS Corporation 3 Rev. 1.00 CL12464FF...
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