Click to expand full text
CL12464FF
LVDS Receiver 24bit FPD-link 85MHz
Introduction
The CL12464FF receiver converts serial four LVDS data streams data back into parallel 28bits (24bits of RGB data and 4bits of HSYNC, VSYNC, DE and Control1) of LVCMOS parallel. The CL12464FF receiver’ outputs are Falling edge clock. The CL12464FF receiver is an ideal means to solve EMI and cable size problems associated with wide, high-speed LVCMOS interfaces.
Feature
■ Input Clock: 20MHz~85MHz Input Data Rate: 140Mbps~595Mbps ■ Output Clock: 20MHz to 85MHz shift clock support ■ Low power single 3.
CL12464FF Datasheet
