FEATURES
n n CDK8307 12/13-bit, 20/40/50/65MSPS, Eight Channel, Ultra Low Power ADC with LVDS GENERAL DESCRIPTION
An integrated PLL multiplies the input sampling clock by a factor of 12 or 14, according to the LVDS output setting. Data and frame synchronization output clocks are supplied for data capture at the receiver. Various modes and configuration settings can be applied to the ADC through the serial control interface (SPI). Each channel can be powered down independently and data format can be selected through this interface. A full chip idle mode can be set by a single external pin. Register settings determines the exact function of this external pin. The CDK8307 is designed to easily interface with field-programmable gate arrays (FPGAs) from several vendors. The very low startup times of the CDK8307 allow significant power reduction in duty-cycled systems, by utilizing the Sleep Mode or Power Down Mode when the receive path is idle. 20/40/50/65MSPS maximum sampling rate Low Powe...
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