NE33200 Datasheet | California Eastern

SUPER LOW NOISE HJ FET Features - VERY LOW NOISE FIGURE: 0.75 d B typical at 12 GHz Optimum Noise Figure, NFOPT (d B) 4 3.5 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 m A 24 21 18 15 12 9 6 NF 0.5 0 1 10 30 3 0 - HIGH ASSOCIATED GAIN: 10.5 d B Typical at 12 GHz - GATE LENGTH: 0.3 µm - GATE WIDTH: 280 µm 3 2.5 2 1.5 1 DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped Al Ga As and undoped In Ga As to create a two-dimensional electron gas layer with very high electron mobility. Its excellent low noise figure and high associated gain make it suitable for mercial and industrial applications. NEC's stringent quality assurance and test procedures assure the highest reliability and performance. Frequency, f (GHz) ELECTRICAL CHARACTERISTICS (TA = 25°C) PART NUMBER PACKAGE OUTLINE SYMBOLS NFOPT1 PARAMETERS AND CONDITIONS Noise Figure, VDS = 2 V, ID = 10 m A, f = 4 GHz f = 12 GHz Associated Gain, VDS = 2 V, ID = 10 m A, f = 4 GHz f = 12 GHz Output Power at 1 d B Gain pression Point, f = 12 GHz VDS = 2 V, IDS = 10 m A VDS = 2 V, IDS = 20 m A Gain at P1d B, f = 12 GHz VDS = 2 V, IDS = 10 m A VDS = 2 V, IDS = 20 m A Saturated Drain Current, VDS = 2 V, VGS = 0 V Pinch-off Voltage, VDS = 2 V, ID = 100 µA Transconductance, VDS = 2 V, ID = 10 m A Gate to Source Leakage Current, VGS = -5 V Thermal Resistance (Channel to Case) UNITS d B d B d B d B d Bm d Bm d B d B m A V m S µA °C/W 15 -2.0 45 MIN 00 (Chip) TYP 0.35 0.75 15.0 10.5 11.2 12.0 11.8 12.8 40 -0.8 70 0.5 10 240 80 -0.2 MAX GA 1 P1d B G1d B IDSS VP gm IGSO RTH(CH-C)2 Notes: 1. RF performance is determined by packaging and testing 10 samples per wafer. Wafer rejection criteria for standard devices is 2 rejects for 10 samples. 2. Chip mounted on infinite heat sink. California Eastern Laboratories Associated Gain, GA (d...