FEATURES
I 400 kHz (2.5 V) and 100 kHz (1.8 V) I2C bus I 1,000,000 program/erase cycles I 100 year data retention H GEN FR ALO EE LE A D F R E ETM compatible I 1.8 to 5.5 volt operation I Low power CMOS technology I 16-byte page write buffer I Industrial and extended temperature ranges I Self-timed write cycle with auto-clear I 8-pin DIP, 8-pin SOIC, 8-pin TSSOP and MSOP packages - “Green” package option available I 256 x 8 memory organization I Hardware write protect DESCRIPTION
Catalyst’s advanced CMOS technology substantially reduces device power requirements. PIN CONFIGURATION DIP Package (P, L) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA BLOCK DIAGRAM SOIC Package (J, W) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SDA START/STOP LOGIC EXTERNAL LOAD DOUT ACK VCC VSS WORD ADDRESS BUFFERS COLUMN DECODERS SENSE AMPS SHIFT REGISTERS TSSOP Package (U, Y) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA XDEC WP CONTROL LOGIC E2PROM MSOP Package (R, Z) DATA IN STORAGE A0 A1 A2 VSS 1 2 3 4 8 7...
Catalyst Semiconductor
