FEATURES
I Fast mode I2C bus compatible* I Max clock frequency: I Industrial and automotive temperature ranges I 5 ms max write cycle time I Write protect feature I 100,000 program/erase cycles I 100 year data retention - 400kHz for VCC = 1.8 V to 5.5 V - 1MHz for VCC = 2.5 V to 5.5 V I Schmitt trigger filtered inputs for noise suppression I Low power CMOS technology I 64-byte page write buffer I Self-timed write cycle with auto-clear – Entire array protected when WP at VIH I 8-pin DIP or 8-pin SOIC(JEDEC) and 8-pin SOIC (EIAJ) DESCRIPTION
Catalyst’s advanced CMOS technology substantially reduces device power requirements. PIN CONFIGURATION DIP Package (P, L, GL) A0 A1 A2 VSS 1 2 3 4 8 7 6 5 VCC WP SCL SDA SOIC Package (J, W, K, X, GW, GX) PIN FUNCTIONS Pin Name A0, A1, A2 SDA SCL WP VCC VSS NC s i D A0 A1 A2 VSS 2 3 4 1 o c 8 7 6 5 VCC WP SCL SDA i t n u n EXTERNAL LOAD VCC VSS SDA BLOCK DIAGRAM d e DOUT ACK CONTROL LOGIC a P t r SENSE AMPS SHIFT REGISTERS WORD ADDRESS BUFFERS COLUMN...
Catalyst Semiconductor
