FEATURES
s 10 MHz SPI compatible s 1.8 to 6.0 volt operation s Hardware and software protection s Low power CMOS technology s SPI modes (0,0 & 1,1)* s Commercial, industrial, automotive and extended s 1,000,000 program/erase cycles s 100 year data retention s Self-timed write cycle s 8-pin DIP/SOIC, 8-pin TSSOP and 8-pin MSOP s 16/32-byte page write buffer s Write protection temperature ranges – Protect first page, last page, any 1/4 array or lower 1/2 array DESCRIPTION
Catalyst’s advanced CMOS Technology substantially reduces device power requirements. In addition to the Chip Select, the clock PIN CONFIGURATION CS SO WP VSS MSOP Package (R, Z, GZ)* SOIC Package (S, V, GV) 1 2 3 4 8 7 6 5 VCC HOLD SCK SI *CAT25C11/03 only PIN FUNCTIONS Pin Name SO SCK WP VCC VSS CS SI i D c s Ground Function Serial Data Output i t n o CS SO WP VSS 1 2 3 4 8 7 6 5 VCC HOLD SCK SI u n CS SO WP VSS input (SCK), data in (SI) and data out (SO) are required to access the device. The HOLD pin may be used to suspend any serial communication without resetting the serial sequence.
Catalyst Semiconductor
